System for Optimizing Semiconductor Yield and enabling Product Traceability throughout Product Life

ABSTRACT

Systems and methods are disclosed for IC fabrication by specifying a process monitor with one or more functional blocks including process monitoring structures and wafer identification and die location data on the wafer; fabricating the functional blocks embedded in the wafer at one or more die locations; capturing functional test measurements during or after fabricating the functional blocks; and predicting device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.

The present invention is related to co-pending application entitled “Monitoring Semiconductor Reliability During Device Life” filed Jun. 5, 2021 with Ser. No. ______, and further claims priority to provisional application Ser. 63/037,309 filed Jun. 10, 2020, the contents of which are incorporated by reference.

BACKGROUND

The present invention is related to the field of semiconductor device design, designing for test, and testing semiconductor devices in a production environment.

Semiconductor devices are tested using commercial ATE (Automated Test Equipment) to determine that the devices meet their respective specifications. Devices may fail to meet device specifications due to (1) errors in the design of the device, (2) wafer processing of the device not meeting the targeted electrical characteristics, or (3) testing of the device does not correctly measure device parameters. One difficulty to analyze device yield is that process characteristics of a given die cannot easily be integrated into the test database for analysis by commercially available data analysis tools. In standard semiconductor processing, the wafer vendor will provide a limited set of transistor and devices measurements in a report called WAT (Wafer Acceptance Test) report to show the wafer is in specification. The WAT does not provide detailed information for the device structures used in the design. The structures on which WAT are made are typically located in the scribe lane between adjacent die or on wafer dropouts. Access to these process device measurements is not available once a device is packaged. In the case of devices being returned due to field failures, it is not possible to correlate the failed units to specific wafers or specific locations on the wafer.

As shown in FIG. 1, the current state of the art ATE testers run a test program and output the measured the results into a database file. Generally, there are several file formats for the test result data base, but the most common are .stdf and .csv. Generally, the WAT (Wafer Acceptance Test) data is provided by the foundry for the sole purpose of confirming the wafer is built to the process specification parameters used by the foundry's customer in the design of the semiconductor product. The WAT data is provided in a .csv format which is readable by excel or another spread sheet. The process monitoring structures are provided either in a drop out die or in the scribe line between dies. shows the wafer (1) and array of die (2) that are imprinted on the wafer. The drop outs for the process control monitors are shown in (3). The process data is sampled only at limited locations on the wafer. The process control monitor is measured prior to wafer shipment and the WAT data is provided for limited locations on the wafer. The process monitor structures for measuring the process parameters are destroyed and no longer available when the wafer is diced and the die are assembled into packaged parts. It is not possible to assign process parameter values of the WAT data to a specific die on the wafer. Also, it is neither possible to access nor measure the process control structures after the die has been assembled.

SUMMARY

In one aspect, systems and methods are disclosed for IC fabrication by specifying a process monitor with one or more functional blocks including process monitoring structures and wafer identification and die location data on the wafer which information is stored om the die in a non-volatile programmable memory; fabricating the functional blocks embedded in the wafer at one or more die locations; capturing functional test measurements during or after fabricating the functional blocks; and predicting device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.

In another aspect, an integrated circuit, includes a process monitor including a plurality of active and passive device structures that characterize a semiconductor manufacturing process; input/output (IO) pads adapted to be accessed by test hardware and control logic; memory such as a programmable e-fuse block and control for programming the e-fuse which identify the wafer and die location at test are integrated into an integrated circuit; and a direct peripheral connection to the process monitor which may be a test interface such as IJTAG or may be a functional peripheral interface so that the process monitor can be read while the device is operating.

In yet another aspect, an automatic test equipment (ATE) includes a wafer with one or more process monitors (PMs) each including a plurality of active and passive device structures that characterize a semiconductor manufacturing process, input/output (IO) pads adapted to be accessed by test hardware and control logic, memory, and control for programming the memory which identify the wafer and die location at test in an integrated circuit; probes coupleable to the wafer to capture PM functional data; and a database to store functional test measurements during or after fabricating the functional blocks, wherein the database predicts device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.

Advantages of the above aspects may include one or more of the following. Semiconductor devices with the PM block can be tested using commercial ATE (Automated Test Equipment) to determine that the devices meet their respective specifications. Devices may fail to meet device specifications due to (1) errors in the design of the device, (2) wafer processing of the device not meeting the targeted electrical characteristics, or (3) testing of the device does not correctly measure device parameters. With the PM data, process characteristics of a given die is easily be integrated into the test database for analysis by commercially available data analysis tools. These process characteristics can be measured by the ATE and the resulting data can be used to build in-situ mathematical models (such as SPICE models, among others) to model circuit performance of circuits contained within the device. The SPICE models can be chip specific. In semiconductor processing, the wafer vendor can provide detailed transistor and devices measurements in the WAT report to show the wafer is in specification. The WAT with the PM can provide detailed information for the device structures used in the design. The PM allow access to process device measurements after a device has been packaged. In the case of devices being returned due to field failures, it is possible to correlate the failed units to specific wafers or specific locations on the wafer. By including a functional block in the chip that includes (1) process monitoring structures, and (2) information related to wafer identification and the location of the die on the wafer, makes possible the following:

(1) An integrated data base that is generated by ATE that can be analyzed by correlation or AI processing to identify device failure modalities and sensitivities to specific process parameters,

(2) Ability to predict device failures based on information of known device failures or related process parameters and their relationship to functional test measurements,

(3) Provide traceability throughout the entire product life cycle of functional parameter measurements and the related process parameters.

By including a functional block in the chip that includes (1) process monitoring structures, and (2) information related to wafer identification and the location of the die on the wafer, makes possible the following:

(1) An integrated data base that is generated by ATE that can be analyzed by correlation or AI processing to identify device failure modalities and sensitivities to specific process parameters,

(2) Ability to predict device failures based on information of known device failures or related process parameters and their relationship to functional test measurements,

(3) Provide traceability throughout the entire product life cycle of functional parameter measurements and the related process parameters.

The system addresses the problems of (1) tracking the semiconductor process parameters during the life of the product, (2) provide traceability of the device throughout the device life cycle, and (3) Predict device failures. As the system receives data on device failures, the data base on which the AI algorithms are based include that new data. So, the AI algorithms can be run to assess new potential device failures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an exemplary semiconductor process test flow.

FIG. 2 shows an exemplary wafer map.

FIG. 3 shows an exemplary process monitor block diagram.

FIG. 4 shows an exemplary process monitor interface for current measurement.

FIG. 5 shows an exemplary design flow for integration of the Process Monitor onto a system on a chip (SoC).

FIG. 6 shows an exemplary final test data of RF Power shown performed at a final test.

DETAILED DESCRIPTION

FIG. 3 shows an exemplary process monitor (PM) in accordance with various aspects of the system. The process monitor includes a plurality of active and passive device structures that characterize a semiconductor manufacturing process. Input/output (IO) pads are provided in the PM to be accessed by test hardware and control logic. In the preferred embodiment, the PM includes a programmable e-fuse block and control for programming the e-fuse which identify the wafer and die location at test are integrated into an integrated circuit.

The process monitor is designed with standard design tools and methodologies. The process monitor is accessed by an automatic test equipment. For example, data from the process monitor is integrated with production test functional and parametric data into a standard data base format. The device structures on the PM block can include transistors, resistors, inductors, and capacitors. a nonvolatile memory block or programmable fuse for storing P-channel data, N-channel data, depletion data, sheet resistivity, contact resistance, via resistance, ring oscillation data, and temperature data. The PM also is accessed by an suitable I/O module to provide direct access including on-chip test interface(s) such as JTAG/IEEE1500 wrapper sequenced and controlled by an ATE. In one implementation, the PM is provided as an SoC that provides structures to measure the process design parameters.

This PM block is instantiated into an ASIC using standard ASIC design processes and methodologies. As shown in FIG. 3, the PM block is designed to be tested in a standard semiconductor production environment with a JTAG/IEEE1500 wrapper that can be sequenced and control by ATE. When in test mode, the ATE equipment through its pin electronics will make voltage and current measurements indicative of the process parameters that are monitored by the PM structures on the chip. These process parameters are data logged onto a common database such as .stdf with the functional measurements included in the wafer probe or final test program. The process monitor block contains metrology to null out parasitic impedance from the parameter selection circuitry.

By including the process structures on die and generating the measurements as a part of the wafer probe and final test programs, a unified data base which includes wafer process data and functional test data for devices be can be developed. Since there is a unique identifier for the die, given as the die location on the wafer, and the wafer, enables semiconductor test data mining tools (for example, Quantix, JMP, etc.) to support analyses of device test failures and confirm any impact due to process parameters. The inclusion of the PM structure with the test bus enables the process parameters to be tested at wafer probe, final test, or at any time that the test bus on the SoC can be enabled.

The PM block under the control of a set of registers in the IEEE1500 test wrapper will select a test structure to be measured. The PM output can be stored in a nonvolatile memory block or programmable fuse for inclusion of the following process data as shown in Table 1 in the SoC:

TABLE 1 Process structures and measurements parameters Structure Measurements P channel min W, mid W, large V_(tp), I_(DSAT), leakage current W thin ox. device N channel min W, mid W, large V_(tn), I_(DSAT), leakage current W, thin ox device P channel (depl implant and V_(tn), I_(DSAT), leakage current other implants) Sheet resistivity (p+, n−, Current measured at fixed voltage N-well, poly, M1-M10 Contact/via resistance (contact, Current measured at fixed voltage via M2 - via M10) NAND/NOR ring osc frequency Temp sensor Junction Temp

Semiconductor devices with the PM block can be tested using commercial ATE (Automated Test Equipment) to determine that the devices meet their respective specifications. Devices may fail to meet device specifications due to (1) errors in the design of the device, (2) wafer processing of the device not meeting the targeted electrical characteristics, or (3) testing of the device does not correctly measure device parameters. With the PM data, process characteristics of a given die is easily be integrated into the test database for analysis by commercially available data analysis tools. In semiconductor processing, the wafer vendor can provide detailed transistor and devices measurements in the WAT report to show the wafer is in specification. The WAT with the PM can provide detailed information for the device structures used in the design. The PM allow access to process device measurements after a device has been packaged. In the case of devices being returned due to field failures, it is possible to correlate the failed units to specific wafers or specific locations on the wafer. By including a functional block in the chip that includes (1) process monitoring structures, and (2) information related to wafer identification and the location of the die on the wafer, makes possible the following:

(1) An integrated data base that is generated by ATE that can be analyzed by correlation or AI processing to identify device failure modalities and sensitivities to specific process parameters,

(2) Ability to predict device failures based on information of known device failures or related process parameters and their relationship to functional test measurements,

(3) Provide traceability throughout the entire product life cycle of functional parameter measurements and the related process parameters.

By including a functional block in the chip that includes (1) process monitoring structures, and (2) information related to wafer identification and the location of the die on the wafer, makes possible the following:

(1) An integrated data base that is generated by ATE that can be analyzed by correlation or AI processing to identify device failure modalities and sensitivities to specific process parameters,

(2) Ability to predict device failures based on information of known device failures or related process parameters and their relationship to functional test measurements,

(3) Provide traceability throughout the entire product life cycle of functional parameter measurements and the related process parameters.

The system addresses the problems of (1) tracking the semiconductor process parameters during the life of the product, (2) provide traceability of the device throughout the device life cycle, and (3) Predict device failures when a failure is confirmed.

FIG. 4 shows the p channel IDSAT test structure device and its interface to the JTAG bus and also the power pads and output pad. The pad output measurement is done by the ATE instrumentation whereby the ATE can operate in one of two modes. (1) Force a voltage and measure a current or (2) force a current and measure a voltage. The output pads in combination with the power pads and ground pads are sufficient to measure the device parameters.

FIG. 4 below shows the internal PM structure to measure IDSAT. Also, note that the structure includes a reference path that is used in this case to identify current flow through the mux from a reference current.

The process monitor block has two elements to be integrated with the SoC. First, there is the gdsii which comprises the following:

-   -   Process structure elements.     -   Integrated metrology and multiplexing hardware     -   IO pads that are committed to the process monitor     -   E-fuse or OTP memory and programming hardware for the memory.

Also, there is an RTL component of the Process Monitor that primarily consists of:

-   -   JTAG control for the process monitor;     -   Test wrapper (e.g. IEEE1500) logic wrapper to control access to         the individual process monitor elements.

The Process Monitor is integrated into the SoC using the standard design tools for chip development as shown in FIG. 5 which shows an exemplary Design Flow for integration of the Process Monitor onto the SoC. The top level PM register transfer language (RTL) includes pads assigned to PM measurements and JTAG on chip control for testing. The PM GDSII database includes PM measure structures and on-chip metrology.

One embodiment runs Test Data analysis and applies machine learning to improve device quality. The system runs the analyses that are enabled given that the process data and test data on a per-part basis is now available. A common data base that links together process data and functional test results facilitate the application of machine learning to address yield issues related to process variation, ability to track to semiconductor product performance over the life of the product, and the ability to predict failures based on the observation of field failures.

Yield optimization due to process can be done. Since the PM includes wafer and die identifiers that show the location (x.y) by die on the wafer, wafer maps can be created that are related to any combination of process and functional test parameters, FIG. 5 below shows a wafer map from one lot of sixteen wafers. The plots below show the range of RF power measured on a packaged device used for medical applications. The white area shows lower power measurement, and the red areas show higher power measurements. The black areas are not tested as these are die that failed at wafer probe. Wafer maps for tests performed at final test that are shown in FIG. 6. In the example of FIG. 6, final test data of RF Power shown performed at final test.

When a device is returned from the field as a failure, and is confirmed as a failure, the device can be tested on the ATE and the output of the process parameters as well as the final test parameters can be obtained. If the failure is due directly to a device failure as opposed to a system issue that caused the device to fail, the PM structure provides for the process parameters to be checked. As the complete history of the device testing is available, changes in process variation and changes in the functional test results can be seen based on the device aging in the system. The devices that were produced can have their production test data searched and also base on the device wafer location, devices with similar process parameters can be checked to see if there is a pattern that would identify other devices that may be suspect to fail.

One or more test patterns or intermediate results produced by any of the disclosed methods, apparatus, and systems can also be stored on one or more computer-readable media as part of the instant methods and techniques and are considered to be within the scope of this disclosure. Computer-readable media storing such test patterns or intermediate results may be accessed and used by a single computer, networked computer (such as those described above), or dedicated testing system (for example, a tester or automatic testing equipment (ATE).

Any of the disclosed methods can be used to generate test patterns in a computer simulation environment wherein test patterns are generated for representations of circuits, which are stored on one or more computer-readable media. For example, the disclosed methods typically use circuit design information (for example, a netlist, HDL description (such as a Verilog or VHDL description), GDSII description, or the like) stored on computer-readable media. For presentation purposes, however, the present disclosure sometimes refers to the circuit and its circuit components by their physical counterpart (for example, gates, primary outputs, paths, and other such terms). It should be understood, however, that any such reference not only includes the physical components but also representations of such circuit components as are used in simulation, ATPG (Automatic Test Pattern Generation), or other such EDA environments.

The foregoing teachings are representative embodiments of methods, apparatus, and systems for quantifying semiconductor fabrication fault diagnosis that should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed methods, apparatus, and systems, alone and in various combinations and subcombinations with one another. The disclosed technology is not limited to any specific aspect or feature, or combination thereof, nor do the disclosed methods, apparatus, and systems require that any one or more specific advantages be present or problems be solved.

Any of the methods, apparatus, and systems described herein can be used in conjunction with a wide variety of scan-based or partially-scan-based circuits and in connection with a wide variety of diagnostic procedures. Further, the fault types identified using test sets generated according to the disclosed techniques need not be of a particular type, but can vary from implementation to implementation (e.g., stuck-at faults, transition faults, hold-time faults, and other faults). For illustrative purposes only, however, many of the examples described herein are explained in the context of generating test sets for detecting stuck-at and timing faults (such as transition faults).

Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may be rearranged or performed concurrently. Moreover, for the sake of simplicity, the figures may not show the various ways in which the disclosed methods, apparatus, and systems can be used in conjunction with other methods, apparatus, and systems. Additionally, the description sometimes uses terms like “determine,” “identify,” and “constrain” to describe the disclosed technology. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms may vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

As used in this application and in the claims, the singular forms “a,” “an” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not altering the intended operation of the circuit.

The disclosed embodiments can be implemented in a wide variety of environments. For example, any of the disclosed techniques can be implemented in software comprising computer-executable instructions stored on computer-readable media (e.g., one or more CDs, volatile memory components (such as DRAM or SRAM), or nonvolatile memory components (such as hard drives)). Such software may comprise, for example, electronic design automation (“EDA”) software (e.g., an automatic test pattern generation (“ATPG”) tool) used to generate test patterns for testing one or more circuits (e.g., an application specific integrated circuit (“ASIC”), a programmable logic device (“PLD”) such as a field-programmable gate array (“FPGA”), or a system-on-a-chip (“SoC”) having digital, analog, or mixed-signal components thereon). Such software may also comprise, for example, EDA software used to diagnose test responses to chain diagnosis test patterns applied to the one or more circuits. These particular software implementations should not be construed as limiting in any way, however, as the principles disclosed herein are generally applicable to other software tools.

Such software can be executed on a single computer or on a networked computer (e.g., via the Internet, a wide-area network, a local-area network, a client-server network, or other such network). For clarity, only certain selected aspects of the software-based implementations are described. Other details that are well known in the art are omitted. For example, it should be understood that the disclosed technology is not limited to any specific computer language, program, or computer. For the same reason, computer hardware is not described in further detail. For example, the disclosed embodiments can be implemented using a wide variety of commercially available computer systems and/or testing systems. Any of the disclosed methods can alternatively be implemented (partially or completely) in hardware (e.g., an ASIC, PLD, or SoC).

Further, test patterns or diagnostic results (including any intermediate or partial test patterns or diagnostic results) produced from any of the disclosed methods can be created, updated, or stored on computer-readable media (e.g., one or more CDs, volatile memory components (such as DRAM or SRAM), or nonvolatile memory components (such as hard drives)) using a variety of different data structures or formats. Such test patterns and/or diagnostic results can be created or updated at a local computer or over a network (e.g., by a server computer).

The one or more integrated circuits being tested may additionally comprise specialized hardware components used to implement the testing (e.g., compression hardware). Such integrated circuits can be used in a vast assortment of electronic devices, ranging from portable electronics (such as cell phones, media players, and the like) to larger-scale items (such as computers, control systems, airplanes, automobiles, and the like). All such items comprising integrated circuits tested with embodiments of the disclosed technology or equivalents are considered to be within the scope of this disclosure.

Moreover, any of the disclosed methods can be used in a computer simulation, ATPG, or other EDA environment, wherein test patterns, test responses, and compressed test responses are determined by or otherwise analyzed using representations of circuits, which are stored on one or more computer-readable media. For presentation purposes, however, the present disclosure sometimes refers to a circuit or its components by their physical counterpart (e.g., scan cells, primary outputs, paths, circuits, and other such terms). It should be understood, however, that any reference in the disclosure or the claims to a physical component includes representations of such circuit components as are used in simulation, ATPG, or other such EDA environments.

Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments, it will be recognized that the illustrated embodiments include only examples and should not be taken as a limitation on the scope of the disclosed technology. Rather, the scope of the disclosed technology for purposes of this application is defined by the following claims and their equivalents. We therefore claim as our invention all that comes within the scope and spirit of these claims and their equivalents. 

What is claimed:
 1. A method for wafer processing, comprising: specifying a process monitor (PM) with one or more functional blocks including process monitoring structures and wafer identification and die location data on the wafer; fabricating the functional blocks embedded in the wafer at one or more die locations; capturing functional test measurements during or after fabricating the functional blocks; and predicting device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.
 2. The method of claim 1, comprising providing traceability throughout the entire product life cycle of functional parameter measurements and related process parameters.
 3. The method of claim 1, comprising tracking the semiconductor process parameters during the life of the product.
 4. The method of claim 1, comprising updating a device failure database when a failure is confirmed.
 5. The method of claim 1, wherein one of the functional blocks comprises a process structure element, Integrated metrology and multiplexing hardware, input/output pads, and a memory element.
 6. The method of claim 5, wherein the memory element comprises an E-fuse or and OTP memory and programming hardware for the memory.
 7. The method of claim 1, comprising providing JTAG control for the process monitor.
 8. The method of claim 1, comprising providing access to the individual process monitor elements.
 9. The method of claim 1, wherein the process monitor comprises a plurality of active and passive devices including transistors, resistor, capacitor device structures that characterize the semiconductor manufacturing process, and a programmable e-fuse block and control for programming the e-fuse which identify the wafer and die location at test are integrated into an integrated circuit.
 10. The method of claim 1, comprising providing metrology with the PM to null out parasitic impedance from a parameter selection circuitry.
 11. An integrated circuit (IC), comprising: a process monitor including a plurality of active and passive device structures that characterize a semiconductor manufacturing process; input/output (TO) pads adapted to be accessed by test hardware and control logic; and a programmable e-fuse block and control for programming the e-fuse which identify the wafer and die location at test are integrated into an integrated circuit.
 12. The IC of claim 11, wherein the process monitor is designed with standard design tools and methodologies comprising providing machine learning of process monitor output.
 13. The IC of claim 11, wherein the process monitor is accessed by an automatic test equipment during production or during an operating life of the IC.
 14. The IC of claim 11, wherein data from the process monitor is integrated with production test functional and parametric data into a standard data base format.
 15. The IC of claim 11, wherein the device structures comprise transistors, resistors, inductors, and capacitors.
 16. The IC of claim 11, wherein the process monitor comprises an SoC that provides structures to measure the process design parameters.
 17. The IC of claim 11, comprising a nonvolatile memory block or programmable fuse for storing P-channel data, N-channel data, depletion data, sheet resistivity, contact resistance, via resistance, ring oscillation data, and temperature data.
 18. The IC of claim 11, comprising direct access of on-chip test interface(s) sequenced and controlled by an external circuit or a test equipment.
 19. An automatic test equipment (ATE) to test a wafer with one or more process monitors (PMs) each including a plurality of active and passive device structures that characterize a semiconductor manufacturing process, input/output (TO) pads adapted to be accessed by test hardware and control logic, memory, and control for programming the memory which identify the wafer and die location at test in an integrated circuit, the ATE comprising: probes coupleable to the wafer and the PM to capture device functional data; and a database to store functional test measurements during or after fabricating the functional blocks, wherein the database predicts device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.
 20. The ATE of claim 19, comprising machine learning code to provide traceability throughout a product life cycle including functional parameter measurements and related process parameters. 